1. Field of the Invention
The present invention generally relates to reduction of noises that may be generated within a semiconductor integrated circuit. More particularly, the present invention relates to a semiconductor integrated circuit including an integrally formed logic circuit that is controlled by clocks. The present invention also relates to a CMOS integrated circuit having a CMOS gate and a latch circuit that transfer data by means of clock control to an input terminal of the CMOS gate.
2. Description of Related Art
As miniaturization and high-integration of a circuit that operates in synchronism with a single phase clock continue to be pursued, semiconductor integrated circuits have suffered with the problem of large power-source noise caused by a large current that momentarily circulates in the circuit. For example, an increase in the potential on a grounding line (e.g., ground bounce) may be caused by the momentary circulation of a large current. This is a major source of circuit malfunction.
In conventional logic integrated circuits with a lower degree of miniaturization and integration, a large amount of current circulates in an output circuit unit thereof. resulting in a substantial amount of noise. Several attempts have been made to reduce the noise. For example, Japanese laid-open patent application HEI 4-219016 describes a method to reduce such a large current. According to this reference, where there are a plurality of output circuits that operate simultaneously, the output circuits are controlled with clocks having phases that are successively shifted by a small amount so that the operation current is time-wise distributed to reduce the power-source noise.
However, the above described method, which focuses on the output circuit, does not provide sufficient countermeasures to reduce the power-source noise for a much larger sized integrated circuit in which many internal logic circuits simultaneously operate. For example, as shown in TABLE 1 below, more countermeasures against the current noise on the internal circuits are required, than those on the output circuit unit, as higher integration continues to be pursued.
TABLE 1 __________________________________________________________________________ FEATURES AS A RESULT OF HIGH FEATURES IN THE PAST INTEGRATION __________________________________________________________________________ BACKGROUND, SIZE OF 10,000 GATES 200,000 GATES INTEGRATION CLOCK SYNCHRONIZED 1,000-2,000 GATES 20,000-40,000 GATES INTERNAL GATES NUMBER OF 50 200 INVERTERS AT OUTPUT UNIT CURRENT BY INTERNAL (1,000-2,000) .times. 1 (10,000-20,000) .times. 1 GATES CURRENT BY OUTPUT 50 .times. 40* = 2,000 200 .times. 40* = 8,000 UNITS CURRENT RATIO 1:2 - 1:1 5:2 - 5:1 (INTERNAL: OUTPUT) __________________________________________________________________________ *Current ratio between internal gate and output gate.
In TABLE 1, the current ratio between an internal gate and an output gate is assumed to be 1:40, and the current is indicated as a relative value between the current in the past and the current in the present. Also, it is assumed that 1/5-1/10 of the internal gates initially operate in synchronism with a clock signal.
Noises are also a problem in CMOS integrated circuits. For example, when the output potential from a CMOS inverter functioning as a CMOS gate changes from an "H" level to a "L" level, or from a "L" level to an "H" level, a PMOS transistor and an NMOS transistor are ON at the same time, and the feedthrough current is drawn from the power supply terminal to the grounding terminal. In particular, a CMOS circuit with a large current capacity that is used as, for example, an output buffer draws a large amount of feedthrough current, resulting in problems such as increased noise and increased power consumption.
To decrease the feedthrough current in a CMOS inverter, the gates may be controlled so that a PMOS transistor and an NMOS transistor do not turn ON at the same time. In this respect, various methods to control the gates have been described. for example, in Japanese Laid-open patent applications HEI 2-123826, HEI 4-207225 HEI 2-62113 and HEI 6-132806.
Japanese Laid-open Patent Applications HEI 2-123826, HEI 4-207225 and HEI 6-132806 describe methods in which gates of a PMOS transistor and an NMOS transistor in a CMOS inverter, that are normally commonly connected to an input terminal CMOS inverter, are separated and independently controlled. Namely, circuit elements such as a delay element and a switch element are inserted between the input gate and the gates of the PMOS transistor and the NMOS transistor. Since these circuit elements are inserted in the path for input signals of the CMOS inverter, where a plurality of CMOS inverters are provided, these circuit elements are required for each of the CMOS inverters in order to perform the same control at each of the CMOS inverters, resulting in a large number of elements and greater complexity.
According to Japanese Laid-open Patent Application HEI 2-62113, gates of a PMOS transistor and an NMOS transistor of a CMOS inverter are commonly connected to an input terminal of the CMOS inverter. A circuit element is inserted between a signal input terminal and each of the gates of the PMOS transistor and the NMOS transistor in order to shift the timing at which these transistors are turned on. However, where there are a plurality of CMOS inverters, a feedthrough current protection circuit element is required for each of the CMOS inverters, and this is not shared with other CMOS inverters. As a result, while noises may be reduced, such a current protection circuit makes it difficult to implement higher integration of an integrated circuit due to the large number of circuit elements.